Abstract
Work aimed at demonstrating feasibility of silicon FET technology at the 0.1μm gate length level and below has produced results which indicate that scaling of FETs to smaller dimensions well beyond what is practiced presently is a trend worth while pursuing. Extrinsic transconductances of over 940μS/μm at 0.07μm gate length and 13ps delay per stage in 0.1μm gate length ring oscillators have been achieved with self-aligned, n-channel, polysilicon-gate FETs fabricated with direct write electron beam lithography of all levels. There is not only clear evidence for velocity overshoot but at the same time it is shown that devices can be built in such a way that such effects translate into improved extrinsic performance.