Statistical analysis and optimization in the presence of gate and interconnect delay variations

Abstract

Increasing variability in gate and wire delays of integrated circuits makes timing verification and optimization very challenging tasks [3]. Variability can be because of manufacturing processes, environmental sources (e.g., temperature or Vdd) or fatigue effects (NBTI and hot electrons). Due to processing steps like CMP (Chemical Mechanical Polishing) or RIE (Reactive Ion Etching), on-chip interconnects have variable width, height and inter-layer dielectric thicknesses. With each generation of technology, the number and proportional impact of these variations is increasing. Worstcasing all sources of variation is not feasible, and statistical timing [4, 1] has proven to be an effective way to deal with this variability. The main advantages of statistical timing are the ability to reduce pessimism compared to exhaustive corner-based timing, and efficient coverage of the entire process space. So-called block-based statistical timing methods [4] are incremental arid therefore can be used in the inner loop of an optimization or physical synthesis flow. This invited presentation will describe how interconnect variations are modeled for statistical timing purposes. The extraction and variational modeling of gate and interconnect delay will be described [7]. Thicker wires are less resistive and reduce interconnect delay at the expense of higher gate delay due to increased capacitance. Thinner wires, on the other hand, increase net delay but provide more resistive shielding. In a statistical timing framework, the critical path is not unique. In fact, each point in the process space: can have a different critical path. In such a scenario, traditional "deterministic" timing margin or slack is not a good metric for improving the timing performance of a design across the entire process space. A new metric called criticality probability [4, 5, 6] is proposed for simultaneous optimization across the entire process space [2]. In summary, a variational delay modeling methodology combined with incremental statistical timing allows for the systematic analysis of circuit, performance in the presence of variability. In addition, diagnostics such as process sensitivities and criticality probabilities will enable the optimization of circuits across the entire process space. Copyright 2006 ACM.