Testing and debugging delay faults in dynamic circuits
Ramyanshu Datta, Sani Nassif, et al.
IEEE ITC 2005
This paper presents a computationally efficient means for estimating parametric timing yield and guiding robust design-for-quality in the presence of manufacturing and operating environment variations. Computational efficiency is achieved by basing the proposed methodology on a post-processing step applied to the report generated as a by-product of static timing analysis. Efficiency is also ensured by exploiting the fact that for small processing/environment variations, a linear model is adequate for capturing the resulting delay change. Meaningful design guidance is achieved by analyzing the timing-related influence of variations on a path-by-path basis, allowing designers perform a quality-oriented design pass focused on key paths. A coherent strategy is provided to handle both die-to-die and within-die variations. Examples from a PowerPC microprocessor illustrate the methodology and its capabilities.
Ramyanshu Datta, Sani Nassif, et al.
IEEE ITC 2005
Anne Gattiker, Sani Nassif, et al.
ISQED 2001
Rouwaida Kanj, Zhuo Li, et al.
ISQED 2008
Rouwaida Kanj, Rajiv Joshi, et al.
ISQED 2007