Asymmetrical SRAM cells with enhanced read and write margins
Keunwoo Kim, Jae-Joon Kim, et al.
VLSI-TSA 2007
Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write operation without using any on-chip or off-chip negative voltage source. Statistical simulations in a 45nm PD/SOI technology show a 103 X} reduction in the Write-failure probability with the proposed method. © 2006 IEEE.
Keunwoo Kim, Jae-Joon Kim, et al.
VLSI-TSA 2007
Rajiv V. Joshi, Saibal Mukhopadhyay, et al.
ESSCIRC 2004
Rahul M. Rao, Jeffrey L. Burns, et al.
ESSCIRC 2003
Aditya Bansal, Rama N. Singh, et al.
ICCD 2008