SOI 90-nm ring oscillator sub-ps model-hardware correlation and parasitic-aware optimization leading to 1.94-ps switching delay

Abstract

This paper reports the SOI 90 nm statistical model to hardware correlation achieved over a broad voltage, temperature and a variety of five different ring oscillators. Monte Carlo simulations were performed and compared with the measured circuit statistical population. A sub-ps Model to Hardware Correlation accuracy was achieved between the mean hardware and simulated delays. Based on the model validation, a parasitic aware layout optimization was performed on a constrained and an unconstrained inverter leading to a 5 and 66 % reduction in delay of the inverter reference circuit. The unconstrained parasitic aware optimization achieves a record inverter switching delay of 1.94 ps. © 2005 IEEE.