SMT and enhanced SPT with Recessed SD to improve CMOS Device Performance

Abstract

For nFET, mechanism of Stress Memorization Technique (SMT) has been investigated. It showed, for the first time, that SMT effect on nFET improvement is not only from poly gate, but also from Si at extension area. For pFET, a novel low cost technique to improve device performance by enhanced Stress Proximity Technique (eSPT) with Recessed SD (ReSD) has been demonstrated for the first time. pFET performance improvement of 40% was demonstrated with eSPT. 15% improvement in ring delay has been demonstrated with optimized eSPT. © 2008 IEEE.