Single-chip 4 TX + 4 RX optical module based on holey SiGe transceiver IC

Abstract

Optical 4 + 4 transceivers based on holey Optochip design using IBM BiCMOS8HP technology have been successfully assembled and characterized. The transceiver Optochip consists of an 8-channel single chip SiGe IC, containing all of the transmitter (TX) and receiver (RX) amplification circuitry, with flip-chip attached 4-channel VCSEL and photodiode arrays. Optical access to the conventional topside emitting 850-nm optoelectronic arrays is achieved through optical vias (holes) integrated into the transceiver IC. A laser ablation process was used to fabricate the 8 optical vias in individual SiGe ICs. For the Optochip assembly, the 2 optoelectronic arrays are sequentially flip-chip soldered to the IC using AuSn solder. The Optochips were subsequently flip-chip soldered to 8 mm × 8 mm high-speed high-density organic carriers forming the complete transceiver module. Electrical I/O is provided through BGA pads on 0.8mm pitch at the bottom of the module while optical access is provided through the 8 optical vias through the backside of the IC. The fully assembled transceiver modules are soldered to a test card for high speed evaluation. The Nelco 4000 test card contains a BGA site in the center for attachment of the optical transceiver module and differential high-speed transmission lines routed from high-speed electrical connectors to the module TX inputs and RX outputs. The optical inputs/outputs to the Optochip are coupled to MMF probes through the optical vias. Eye-diagrams were measured for TX outputs as well as TX-to-RX links at data rates 20 Gb/s to 38 Gb/s. Measurements on all 8 optical links between 2 transceiver modules showed all operate error free (BER < 10 -12) up to 36 Gb/s. This record per channel data rate for a parallel optical transceiver is achieved using feed forward equalization (FFE) circuitry incorporated in the SiGe IC. At 36 Gb/s, the transceiver module achieves a bidirectional aggregate bandwidth of 144 Gb/s with power efficiency of 20 pJ/bit for each TX-RX link. © 2013 IEEE.