A 50 to 400 mbit/sec single chip fiber optic receiver circuit
Dennis L. Rogers, Albert X. Widmer, et al.
Proceedings of SPIE 1989
A CMOS chip containing four 500-MBd serializer/deserializer pairs has been designed to relieve interconnect congestion in an ATM switch system. The 9.7 × 9.7 mm2 chip fabricated in a 0.8-μm technology is packaged on a ceramic ball grid array and dissipates 3.5 W. It replaces a 72-wire parallel interface with an eight-line serial interface transparent to the user and supports transmission at 1.6 Gb/s per direction in full-duplex mode. Virtually error-free operation in a system environment over electrical serial links having up to 9 dB loss at 500 MHz has been realized using signal predistortion for the serial bit stream and PLL clock recovery for each of the four receivers. Interface timing and serial-link driver strength are programmable.
Dennis L. Rogers, Albert X. Widmer, et al.
Proceedings of SPIE 1989
Herschel A. Ainspan, Charles S. Webster, et al.
ESSCIRC 1998
Mehmet Soyuer, Herschel A. Ainspan, et al.
Proceedings of the IEEE
Scott K. Reynolds, Brain A. Floyd, et al.
IBM J. Res. Dev