Simultaneous switching noise projection for high-performance SOI chip design

Abstract

This paper describes the circuit modeling techniques to predict on-chip simultaneous switching noise for high performance SOI circuits. The analysis includes both the inductive ΔI noise on the package level and the resistive I R drops on the chip level. By identifying the hot spots on the chip and ΔV across the chip, designers can optimize the placement of on-chip decoupling capacitors and effectively minimize the switching noise for SOI chips.