Reuse in system-level stimuli-generation

Abstract

This paper reports on the verification models of twelve systems including servers and advanced processors. We focus on system-level stimuli generation and study reuse in subsequent system models. The paper describes our modeling framework, where systems are modeled mainly by declarative constructs with some procedural code. Separate test specifications are used to direct stimuli generation, but are not studied in this paper. We find that a high level of white-box reuse reduces costs and allows starting the verification process early. This result reflects gradual evolution of the systems we study and the effectiveness of the declarative modeling scheme. We discuss the possible influence of libraries of system-level constructs on reuse in languages such 'e', Vera, and SystemVerilog. © 2005 IEEE.