David Brooks, Pradip Bose, et al.
IBM J. Res. Dev
Caches use data very differently than main memory does, so dram caches can have dramatically different refresh requirements. Making canonical assumptions about retention times in dram can be drastic overkill within the cache context. Using standard refresh rates may be unnecessary, and can be a significant waste of cache utilization and power. In this article, we view “retention time” in a new way by using statistical populations more appropriate for caches, and we suggest uses of a cache's inherent error-control mechanisms to reduce refresh rates by several orders of magnitude. © 2008, IEEE. All rights reserved.
David Brooks, Pradip Bose, et al.
IBM J. Res. Dev
David R. Kaeli, Philip G. Emma
IEEE TC
Viji Srinivasan, David Brooks, et al.
MICRO 2002
Peter J. Klim, John Barth, et al.
IEEE Journal of Solid-State Circuits