Reducing power consumption during TLB lookups in a PowerPC/spl trade/ embedded processor

Abstract

We present a microarchitectural-level low-power translation lookaside buffer (TLB) design for embedded system applications. High-performance embedded processors with small micro-TLBs frequently encounter a large number of micro-TLB misses and many types of context switches such as internal and external interrupts. Context switches flush the micro-TLBs and therefore cause a number of unified-TLB accesses for address translation. Our method presents a microarchitecture wherein the power dissipation associated with unified-TLB accesses is minimized. In addition, our technique enables large process ID register sizes which can reduce the operating system software overhead. Our experiments using specINT 2000 benchmarks show that we obtain an average power saving of 36% in the content addressable memory (CAM) comparisons for these accesses. © 2005 IEEE.