Conference paper
Cellular supercomputing with system-on-a-chip
G. Almasi, G. Almasi, et al.
ISSCC 2002
The architecture of a new class of computers, optimized for lattice QCD calculations, is described. An individual node is based on a single integrated circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor communications and additional control and diagnostic circuitry. The machine's name, QCDOC, derives from "QCD On a Chip". © 2001 Elsevier Science B.V. All rights reserved.
G. Almasi, G. Almasi, et al.
ISSCC 2002
P.A. Boyle, D. Chen, et al.
Nuclear Physics B - Proceedings Supplements
P.A. Boyle, D. Chen, et al.
SciDAC 2005
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Physical Review D - Particles, Fields, Gravitation and Cosmology