Prediction of high-performance on-chip global interconnection

Abstract

Different interconnection structures have been proposed to solve the performance limitation caused by scaling of on-chip global wires. In this paper, we give an overview of current on-chip global interconnection structures and provide a simple model to analyze their architecture-level performance metrics. For a new category of global interconnections using on-chip transmission-line (T-line), a general framework is proposed to design and optimize such schemes. A group of experiments is performed to study and compare five different global interconnection structures in terms of latency, energy dissipation, throughput, and signal integrity across multiple technology nodes. The results show that, the T-line structures have the potential to outperform repeated RC wires at future nodes to achieve high-performance, low-power and more reliable global interconnection. Meanwhile, equalization could be helpful to improve the throughput, signal integrity, and power efficiency further. Copyright 2009 ACM.