G. Almasi, G. Almasi, et al.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
A novel technique to significantly improve the performance of a design by the movement of sets of gates during or after timing driven placement is proposed. A method to identify optimal set of circuit (gate) movements to enhance timing is presented. Experimental results with a min-cut placement tool indicate that the proposed approach of direct manipulation of circuit locations, significantly improves the timing of large partitions of a chip.
G. Almasi, G. Almasi, et al.
Digest of Technical Papers - IEEE International Solid-State Circuits Conference
John F. Beetem, P. Debefve, et al.
ICCD 1983
Prabhakar Kudva, Ganesh Gopalakrishnan, et al.
DAC 1996
Sandip Kundu, Leendert M. Huisman, et al.
IEEE ITC 1992