Voltage binning under process variation
Vladimir Zolotov, Chandu Visweswariah, et al.
ICCAD 2009
In the face of increased process variations, at-speed manufacturing test is necessary to detect subtle delay defects. This procedure necessarily tests chips at a slightly higher speed than the target frequency required in the field. The additional performance required on the tester is called test margin. There are many good reasons for margin, including voltage and temperature requirements, incomplete test coverage, aging effects, coupling effects, and accounting for modeling inaccuracies. By taking advantage of statistical timing, this paper proposes an optimal method of test margin determination to maximize yield while staying within a prescribed shipped product quality loss limit. If process information is available from the wafer testing of scribe-line structures or on-chip process monitoring circuitry, this information can be leveraged to determine a per-chip test margin which can further improve yield. © 2006 IEEE.
Vladimir Zolotov, Chandu Visweswariah, et al.
ICCAD 2009
Jinjun Xiong, Vladimir Zolotov, et al.
ISPD 2006
Ketan Date, Keven Feng, et al.
HPEC 2017
Bowen Cheng, Uiuc Uiuc, et al.
ICCV 2019