OPTIMAL CHAINING OF CMOS TRANSISTORS IN A FUNCTIONAL CELL.

Abstract

An algorithm that maps a CMOS circuit diagram into an area-efficient, high-performance layout in the style of a transistor chain is described. This algorithm is intended for the generation of basic cells in a custom or semicustom design environment. It is superior to other published algorithms of this kind in terms of the class of input circuits it accepts, its efficiency, and the quality of the results it produces. Such an algorithm can serve as the basis for a powerful cell generation tool that will assume the task of mask definition.