Robust level converter design for sub-threshold logic
Ik Joon Chang, Jae-Joon Kim, et al.
ISLPED 2006
One of the most aggressive uses of dynamic voltage scaling is timing speculation, which in turn requires fast correction of timing errors. The fastest existing error correction technique imposes a one-cycle time penalty only, but it is restricted to two-phase transparent latch-based pipelines. We perform one-cycle error correction by gating only the main latch in each stage of the pipeline that precedes a failed stage. This new method is applicable to widely used clocking elements, such as flip-flops and pulsed latches. Because it prevents inputs arriving at a stage, which is stalled, it can also be used in pipelines with multiple fan-in, fan-out, and looping. Simulations show an energy saving of 8%-12% with a target throughput of 0.9 instructions per cycle, and 15%-18% when the target is 0.8.
Ik Joon Chang, Jae-Joon Kim, et al.
ISLPED 2006
Chris Hyung-Il Kim, Jae-Joon Kim, et al.
IEEE Transactions on VLSI Systems
Niladri Narayan Mojumder, Saibal Mukhopadhyay, et al.
VTS 2008
Chris H. Kim, Hari Ananthan, et al.
IEEE International SOI Conference 2004