On the design of a multigigabit ip router

Abstract

The emergence of gigabit speed networks hinges upon the existence of high performance internetworking units, such as JP routers. In this paper, we present an architecture and we discuss the implementation of a multigigabit JP router. For this implementation, two special purpose VLSI chips are required; the rest can be built using off-the-shelf components. JP header processing of received packets is handled by a specialized chip. Memory management, another well-known performance bottleneck, is simplified and efficiently implemented using special VLSI support. Searching for the next hop address in the routing table, which is the major contributor to the delay in traditional JP protocol implementations, is significantly reduced by using a special configuration of Content Addressable Memories (CAMs). © 1994 IOS Press and the authors.