Multiplierless Implementations of MF/DTMF Receivers

The ever-increasing use of VLSI in telecommunications systems is leavening the search of new algorithms for task realizations suited to VLSI implementations of systems. Toward this search, the paper presents implementations for MF/DTMF receivers, which are based on multiplierless basic filters or primitive VLSI cells such as (1 + z -n), (I - z -n, and (1 ± z-n + z-2n). These implementations require parallel processing and are designed to meet the requirements of a switching system. © 1984 IEEE