Multi-stack optimization for data-path chip (microprocessor) layout

Abstract

The authors describe a special multistack structure, optimization techniques, and algorithms to partition, place, and wire data-path macros in the form of the multistack structure, taking into account the connectivity of the entire chip logic (data-path, control logic, chip drivers, on-chip memory). The overall objective is: (1) to fit the circuits within the chip, (2) to ensure data-path wirability, including stack to random logic wirability, and (3) to minimize wire lengths for wirability and timing. A tool for automatic multistack optimization has been implemented and applied successfully to the layout of some high-density data-path chips.