Model to hardware matching: For nano-meter scale technologies

Abstract

Our ability to reliably predict the outcome of a semiconductor manufacturing process has been steadily deteriorating. This is happening because of two important factors. First, the overall CMOS technology slowdown has led to rapidly increasing complexity in the process and in its interaction with design. This has in turn caused an increase in the number and magnitude of systematic sources of mismatch between simulation models (both at the Technology-CAD and at the circuit simulation levels) and hardware measurements. Second, manufacturing variability resulting from random as well as systematic phenomena -long a source of concern only for analog design- is becoming important for digital design as well and thus its prediction is now a first order priority. Process complexity and the challenges of accurately modeling variability have conspired to increase the error in performance predictions, leading to a gap in model to hardware matching. In this paper, we will review these issues and show examples of potential solutions to this problem some of which are currently being developed in IBM, and some which are longer term and would benefit greatly from the attention of the academic community. © 2006 IEEE.