Model reduction for PEEC models including retardation

Abstract

Partial Element Equivalent Circuits (PEEC) are applied by many for modeling interconnects in packages. These models are suitable for a wide range of three-dimensional problems. When PEEC models are applied to large packages, large equivalent circuits are generated. Model reduction techniques for PEEC models have been proposed by several researchers but typically for problems where retardation is not important or where two-dimensional models suffice. In this paper we give a new model reduction procedure applicable to full wave PEEC models which include losses and retardation. We include two examples to demonstrate the application of this method.