Mismatch Sensitivity of A Simultaneously Latched CMOS Sense Amplifier

Abstract

This paper derives a new formula for the sensitivity of a vertically matched CMOS sense amplifier, of the type used in DRAM's, to threshold voltage mismatch, parasitic capacitance mismatch, transconductance mismatch, and bit-line load capacitance mismatch. The formula yields insight into DRAM sensing operation. The perturbation approach used here is novel and rigorous and yields an explicit closed-form solution. The formula agrees well with simulations. It is inherently slightly conservative and thus appropriate for use in design. © 1991 IEEE