Methodology for trench capacitor etch optimization using voltage contrast inspection and special processing

Abstract

Embedded DRAM will play a much larger part in IBM server microprocessors for new SOI technologies. Etch of a deep trench (DT) into the substrate, which is used to form the capacitor, is a complicated multi-step process. One of the key elements is etch of the buried oxide layer. Voltage contrast (VC) inspection is used to detect defective DTs and can differentiate between opens in the buried oxide and those in the oxide hard mask. So these defects have a VC signal, special processing is needed to seal off the SOI layer. The process of finding the right beam conditions to detect the opens in the buried oxide, which are very subtle, is described. Failure analysis of these defects is also presented. © 2010 IEEE.