Conference paper
Optimal chaining in expression trees (Preliminary Version)
David Bernstein, Haran Boral, et al.
SIGPLAN Symposium on Compiler Construction 1986
Computer cache memory simulations consume a lot of resources, both in terms of disk space and CPU time. A statistical approach to this problem is proposed in which program traces are sampled at certain intervals, significantly reducing the required computer resources. Using, both the mathematical analysis and experimentation, we show that this approach can achieve a high accuracy in predicting the hit and miss ratios for cache simulations. Copyright © 1996 by Marcel Dekker, Inc.
David Bernstein, Haran Boral, et al.
SIGPLAN Symposium on Compiler Construction 1986
Shmuel Gal, Willard Miranker
Journal of Combinatorial Theory, Series A
David Bernstein, Michael Rodeh
PLDI 1991
Nissim Francez, Michael Rodeh
IEEE Transactions on Software Engineering