Manufacturability aware routing in nanometer VLSI

Abstract

This monograph surveys key research challenges and recent results of manufacturability aware routing in nanometer VLSI designs. The manufacturing challenges have their root causes from various integrated circuit (IC) manufacturing processes and steps, e.g., deep sub-wavelength lithography, random defects, via voids, chemical-mechanical polishing, and antenna effects. They may result in both functional and parametric yield losses. The manufacturability aware routing can be performed at different routing stages including global routing, track routing, and detail routing, guided by both manufacturing process models and manufacturing-friendly rules. The manufacturability/yield optimization can be performed through both correct-by-construction (i.e., optimization during routing) and construct-by-correction (i.e., post-routing optimization). This monograph will provide a holistic view of key design for manufacturability issues in nanometer VLSI routing. © 2010.