Machine Learning Techniques for Pre-CTS Identification of Timing Critical Flip-Flops

Abstract

The timing criticality of flip-flops is a key factor for combinational circuit timing optimization and clock network power reduction, both of which are often performed prior to CTS (Clock Tree Synthesis) and routing. However, timing criticality is often changed by CTS/routing and therefore optimizations according to pre-CTS criticality may deviate from the correct directions. This work investigates machine learning techniques for pre-CTS identification of post-routing timing critical flip-flops. Experimental results show that the ML-based early identification can achieve 99.7% accuracy and 0.98 area under ROC (Receiver Operating Characteristic) curve, and is 62000 times to 73000 times faster than the estimate with CTS and routing flow on average. Our method is almost 8 times faster than a state-of-the-art approach of ML-based timing prediction.