W.C. Tang, H. Rosen, et al.
Journal of Applied Physics
A 10 GHz multiphase phase-locked loop (PLL) implemented in 90 nm bulk CMOS technology is presented that uses a bootstrapped NMOS inverter oscillator to obtain steeper clock edges, which may yield an improved jitter performance. The measured values for the rms and peak-to-peak jitter are better than 1 and 7 ps, respectively. © IEE 2005.
W.C. Tang, H. Rosen, et al.
Journal of Applied Physics
F.R. Gfeller, P. Buchmann, et al.
IEEE Photonics Technology Letters
P. Buchmann, M. Benedict, et al.
LEOS 1990
F.R. Gfeller, P. Buchmann, et al.
ISLC 1992