LAYOUT COMPILATION OF LINEAR TRANSISTOR ARRAYS.

Abstract

Some algorithmic ideas are described that are useful in the translation of an and-or switching function into a linear transistor array. A linear transistor array is a sequence of MOS transistors in which two subsequent transistors share a diffusion region not shared by any other pair. These arrays can be used to realize switching networks. These ideas are worked out for the case where realizability in such an array is achieved by duplicating the minimum number of transistors. Cases where similar ideas work are also mentioned.