Recursive bisection based mixed block placement
Ateen Khatkhate, Chen Li, et al.
ISPD 2004
This paper studies interconnect sizing and spacing (ISS) problem with consideration of coupling capacitance for performance optimization of single or multiple critical nets. We introduce the formulation of symmetric and asymmetric wire sizing. We develop efficient bound computation algorithms for ISS optimization and prove their optimality under general interconnect resistance and capacitance models. Our experiments show that our algorithms are very effective and obtain significant performance improvement compared to previous wire-sizing/spacing algorithms.
Ateen Khatkhate, Chen Li, et al.
ISPD 2004
Yiyu Shit, Wei Yao, et al.
ASP-DAC 2009
Ameya Ramesh Agnihotri, Satoshi Ono, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Yiyu Shi, Jinjun Xiong, et al.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems