Improved approximations of crossings in graph drawings and VLSI layout areas

Abstract

We give improved approximations for two classical embedding problems: (i) minimizing the number of crossings in a drawing of a bounded degree graph on the plane; and (ii) minimizing the VLSI layout area of a degree four graph. These improved algorithms can be applied to improve a variety of VLSI layout problems. Our results are as follows. (i) We compute a drawing on the plane of a bounded degree graph in which the sum of the numbers of vertices and crossings is O(log3 n) times the optimal minimum sum. This is a logarithmic factor improvement relative to the best known result. (ii) We compute s VLSI layout of a degree four graph in a grid with constant aspect ratio the area of which is O(log4 n) times the optimal minimum layout area. This is an O(log2 n) improvement over the best known long standing result.