IBM z14 design methodology enhancements in the 14-nm technology node

Abstract

In designing the IBM z14 microprocessor chipset, we discarded many of our previous assumptions and processes in favor of newer, more radical approaches. These new approaches were the result of learning from previous designs as well as this design's performance and schedule requirements. In this paper, we discuss some of the more significant changes to our methodology, including a dramatic departure from our very hierarchical integration design style to a flatter, more nimble approach. We also discuss improvements to our design's power management architecture for managing power-supply noise. Finally, we discuss changes to our simulation environment, targeted at increasing both the number of simulation cycles and simulation logic coverage.