H. Ling, J. Colombo, et al.
Review of Scientific Instruments
Paper
High-Speed Computer Multiplication Using a Multiple-Bit Decoding Algorithm
Abstract
This paper presents a method of performing the binary multiplication beyond the scheme of multiple ADD and SHIFT. The binary multiplication algorithm will be discussed first, followed by block decoding method, logic implementation, hardware consideration, and two examples which are at the end of the discussion. Copyright © 1970 by The Institute of Electrical and Electronics Engineers, Inc.