Keunwoo Kim, Ching-Te Chuang, et al.
International Journal of Electronics
Novel high-density logic-circuit techniques employing independent-gate controlled double-gate (DG) devices are proposed. The scheme utilizes the threshold-voltage (VT) difference between double-gated and single-gated modes in a high-VT DG device to reduce the number of transistors required to implement the stack logic. In a series-connected stack portion of the logic gate, the number of transistors is halved, thus substantially improving the area/capacitance and the circuit performance. The scheme can be easily implemented by a DG technology with either a metal gate or a polysilicon gate. Six-way logic can be implemented with the proposed scheme using only six transistors. The viability and performance advantage of the scheme are validated via extensive mixed-mode physics-based numerical simulations. © 2006 IEEE.
Keunwoo Kim, Ching-Te Chuang, et al.
International Journal of Electronics
Keunwoo Kim, Jae-Joon Kim, et al.
VLSI-TSA 2007
Hung Ngo, Keunwoo Kim, et al.
VLSI-TSA 2006
Keunwoo Kim, Jerry G. Fossum, et al.
International Journal of Electronics