GaAs MESFET 16 × 16 crosspoint switch at 1700 Mbits/sec

Abstract

A GaAs MESFET 16 × 16 crosspoint switch has been fabricated on a 3-mm × 4-mm chip using a 1-μm super buffer logic (SBL) design containing approximately 10000 FETs and operating at 800 mW of power. A 99% confidence bit error rate (BER) better than 1 × 10-3 was obtained at 1.7 Gb/s rate using a 27 -1 pseudorandom NRZ (nonreturn-to-zero) sequence. The BER test was done on one path using a probe card. The chip had 255 out of 256 good crosspoints. The bad crosspoint was a repeating error from a mask defect. An advanced refractory-gate MESFET process was used to fabricate the chip. A lightly doped drain structure was used to reduce parasitic gate capacitance while maintaining acceptable source resistance, to reduce short-channel effects, to increase breakdown voltage compared to devices where the heavy source/drain implant is directly self-aligned to the gate edge.