Fine-grain real-time reconfigurable pipelining

Abstract

In many computations, average data rates are often significantly lower than the peak rate possible. Consequently, VLSI systems capable of processing data at a maximum specified rate can be excessively dissipative when data rates are low. Such inefficiencies are particularly pronounced in heavily pipelined designs, in which registers account for the bulk of energy dissipation in a system. This paper describes a novel methodology for designing reconfigurable pipelines that achieve very low power dissipation by adapting their resources to their computational requirements. In our fine-grain reconfigurable pipelines, energy is saved by disabling and bypassing an appropriate number of pipeline stages whenever data rates are low. In contrast, coarse-grain approaches, such as dynamic voltage scaling, are often unable to capture savings from short-time-scale variations in throughput requirements because of the long time needed to reconfigure the voltage. To evaluate our methodology, we designed an inverse discrete cosine transform (IDCT) module for MPEG-2. Our IDCT included pipelined multipliers that were dynamically reconfigurable on the basis of the number of nonzero coefficients per block and picture size. In comparison with conventional multipliers in corresponding IDCT implementations, our reconfigurable multipliers dissipated about 12-65% less power.