A compact low-power 3D I/O in 45nm CMOS
Yong Liu, Wing Luk, et al.
ISSCC 2012
We introduce a single-loop PLL that operates in a narrower-bandwidth, integer- mode during phase lock and in a wider-bandwidth, fractional-N mode during transient. This hybrid PLL, as a generalization of the conventional variable-bandwidth PLL that shins only its bandwidth, simultaneously achieves the fast-locking advantage of the fractional-N PLL and design simplicity of the integer-N PLL, and as such, brings benefits in certain important PLL applications. In addition, the frequency division mode switching, unique in the hybrid PLL, enables a new, more digital protocol to execute bandwidth switching. A CMOS IC prototype attests to the validity of the proposed approach. © 2008 IEEE.
Yong Liu, Wing Luk, et al.
ISSCC 2012
Timothy O. Dickson, Yong Liu, et al.
CICC 2014
Timothy O. Dickson, Yong Liu, et al.
IEEE JSSC
Nan Sun, Yong Liu, et al.
ESSCIRC 2012