Suhwan Kim, Conrad H. Ziesler, et al.
IEEE Transactions on VLSI Systems
A novel power gating structure is proposed for low-power, high-performance VLSI. This power gating structure supports an intermediate power saving mode as well as a traditional power cut-off mode. To evaluate our power gating structure, we design and fabricate three different macros in 0.13 μm CMOS bulk technology. Our measurement results show that the additional intermediate power-mode allows us to cover various power-performance trade-off regimes, compared to conventional power gating structures.
Suhwan Kim, Conrad H. Ziesler, et al.
IEEE Transactions on VLSI Systems
Visvesh Sathe, Conrad Ziesler, et al.
SOCC 2004
C.H. Ziesler, Joohee Kim, et al.
SOCC 2003
Phillip Chin, Charles A. Zukowski, et al.
Integration, the VLSI Journal