Experimental and theoretical analysis of factors causing asymmetrical temperature dependence of v_t in High-k Metal gate CMOS with capped High-k techniques

Abstract

Temperature (T) dependence of threshold voltage (Vt) for High-k Metal gate stack (HK/MG) CMOS is investigated thoroughly. It is found, for the first time, that T dependence of Vt (dVt/dT) for HK/MG CMOS shows asymmetrical behavior between N and PFETs unlike conventional PolySi/SiON CMOS. Moreover, this dVt/dT asymmetry is observed even if capping techniques for Vt tuning are applied to High-k dielectrics. The position of effective Fermi level in HK/MG (EFM,eff) is determined quantitatively in a wide range of T by experimental and theoretical analysis for the first time, which reveals that the off-center arrangement of EFM,effin Si band gap is the cause of dVt/dT asymmetry not only in the long channel region but also in the short channel region. In addition, based on these analyses, dVt/dT for aggressively thinned FinFETs with HK/MG is predicted.