Evaluation of sSOI wafers for 22nm node and beyond

The transition to fully-depleted (FD) transistor technology is taking place today, either towards planar architectures on SOI wafers [1] or towards 3D-like architectures (FinFET or Trigate) [2]. The reason for this change is better electrostatic control, and reduction or even complete elimination of random dopant fluctuations, leading to much improved Vt variability. © 2012 IEEE.