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Publication
EOS/ESD 2014
Conference paper
ESD device performance analysis in a 14nm Fin FET SOI CMOS technology: Fin-based versus planar-based
Abstract
We present ESD device results from a 14nm FinFET SOI CMOS technology. Both fin-based and planar-based approaches are evaluated, with the planar-based diode design achieving 7 times higher failure current per silicon area. Planar-based diodes also show 25% higher failure current when Tsi increases by 40%.