Conference paper
Design methodology for semi custom processor cores
Victor Zyuban, Anne-Marie Haen, et al.
GLSVLSI 2004
Paper
Environment for powerPC microarchitecture exploration
Abstract
A novel, high-speed, execution-driven (performance-only) simulator that achieves an order of magnitude speedup over prior PowerPC processor timers within IBM is described. Called Microarchitecture Exploration Toolset (MET), the model is amenable to validation against a pre-register-transfer-level (RTL) reference model by using systematically generated performance test cases. The MET's main tools include Turandot, Aria, and trace readers for various trace formats. By using exploration examples, it is shown that MET allows users to calibrate a model quickly, without losing its innate speed efficiency.
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ISSCC 2024