Enhanced performance of accumulation mode 0.5 μ m CMOS/SOI operated at 300 K and 85 K

Abstract

A 0.5 μ m fully depleted CMOS on thin SOI (silicon-on-insulator) VLSI technology has been developed for SRAM and logic applications. Using a normally off, accumulation mode SOI device design with the source/drain/substrate having the same doping polarity, the device transconductance, mobility, and gate delay are improved by 40% over conventional enhancement mode devices. By cooling the devices to liquid nitrogen temperature, both n-and p-channel devices show improvement in mobility and transconductance, reduction of subthreshold slopes, and an increase of breakdown voltages from the floating substrates.