Enabling technologies for wafer-level bonding of 3D MEMS and integrated circuit structures

Abstract

In this paper we describe several critical aspects of wafer scale or die level bonding to demonstrate: 1) low temperature bonding for planar layer interconnections, 2) low temperature bonding for non-planer layer sealing, 3) alignment and transfer of process sub-assemblies such as BEOL wiring, MEMS cavity or active device structures, and 4) integration methodology for fabrication of these layer stacks into 3D circuits and MEMS. We also show examples of how layer stacking protocols using wafer bonding technology provides a capability to integrate mixed materials and technologies potentially adaptable to many other applications. In addition, we demonstrate that in order to evaluate the influence of bonding on the electrical integrity of the transferred ICs, the state-of-the art circuits, such as short channel length MOSFETs or ring oscillators, should be tested as they are most sensitive to environmental/processing changes.