Electrostatic discharge (ESD) protection in silicon-on-insulator (SOI) CMOS technology with aluminum and copper interconnects in advanced microprocessor semiconductor chips

Abstract

The electrostatic discharge (ESD) robustness in silicon-on-insulator high-pin- count high-performance semiconductor chips is investigated. CMOS-on-SOI ESD protection networks were first constructed in a 2.5 V CMOS logic technology with a 0.25 μm effective channel length technology. A second advanced 330 MHz 1.8 V RISC-based microprocessor was mapped from bulk CMOS to SOI technology. The ESD results demonstrated that sufficient ESD protection levels are achievable in SOI microprocessors using lateral ESD SOI polysilicon-bound gated diodes without the need for additional masking steps, process implants or ESD design area.