Effects of wafer cleaning reduction on metals removal and ultrathin gate oxide quality

Abstract

The drive to reduce chemical consumption for cost savings is high in the semiconductor industry. Recently, studies have shown that the traditional 1:1:5 ratios of the SC1, SC2 cleans can be reduced and still maintain good cleaning. The optimization of process parameters must be done in accordance with the type of cleaning tool. Processes in wet decks may be optimized differently from single chamber tools, especially if extended bath lifetimes are expected. In this study, temperature reduction and dilution of the SC1 and SC2 cleans in a wet deck are examined for their effects on metals removal efficiency from silicon surfaces as measured by TRXRF. For an HF, SC1, SC2 sequence, good metal removal can be maintained by dropping the SC1 temperature down to 35 °C and chemical ratio to 1:1:40. At too low an SC1 dilution and temperature, the Cu removal efficiency drops. In SC2, good metals removal remains without peroxide and a lower limit for HCl is determined. It is also found that peroxide must be reduced if HCl is reduced in SC2, otherwise metals plating out from SC1 cannot be removed effectively. To understand the impact of these reduced cleans on gate oxide integrity, the electrical properties of 30 A gate oxides grown using these experimental pre-gate cleans is discussed.