John D. Cressler, James Warnock, et al.
IEEE Electron Device Letters
This paper presents 8-tap and 10-tap, 6-b filters designed to provide PR-IV channel equalization at data rates in excess of 20 megabyte/s. Achieving high sampling rates while reducing power and area required an optimized distributed-arithmetic (DA) architecture combined with custom circuit design and layout. These filters improve attainable data rate by 40% while reducing macro area by 20% compared with standard-cell-designed filters using the same architecture and technology. © 1995 IEEE
John D. Cressler, James Warnock, et al.
IEEE Electron Device Letters
Sophie Verdonckt-Vandebroek, Emmanuel F. Crabbé, et al.
IEEE Electron Device Letters
Scott K. Reynolds, Brian A. Floyd, et al.
IEEE Journal of Solid-State Circuits
Scott K. Reynolds, Brain A. Floyd, et al.
IBM J. Res. Dev