Conference paper
On-chip spectrum analyzer for analog built-in self test
Anup P. Jose, Keith A. Jenkins, et al.
VTS 2005
This paper presents 8-tap and 10-tap, 6-b filters designed to provide PR-IV channel equalization at data rates in excess of 20 megabyte/s. Achieving high sampling rates while reducing power and area required an optimized distributed-arithmetic (DA) architecture combined with custom circuit design and layout. These filters improve attainable data rate by 40% while reducing macro area by 20% compared with standard-cell-designed filters using the same architecture and technology. © 1995 IEEE
Anup P. Jose, Keith A. Jenkins, et al.
VTS 2005
Bodhisatwa Sadhu, Scott K. Reynolds
CSICS 2017
Bodhisatwa Sadhu, Yahya Tousi, et al.
IEEE JSSC
John J. Pekarik, Jim Adkisson, et al.
BCTM 2014