Digital-Assisted Analog In-Memory Computing with RRAM Devices

Abstract

In-memory computing (IMC) has been proposed as a solution to accelerate deep neural networks (DNNs) and other machine learning algorithms. RRAM-based IMC accelerators combine memory access and computation into the same array structure, saving a significant amount of chip area. However, the output from RRAM crossbar array requires an analog-to-digital converter (ADC) for further processing which causes the accuracy drop, extra power dissipation, and area overhead. In addition, the RRAM device also suffers from several nonidealities that degrade the accuracy. In this work, we propose a digital-assisted analog IMC architecture that combines analog RRAM-based IMC with the digital SRAM macro, using a programmable shifter, to compensate for the accuracy loss from ADC and the RRAM variations. By adding the precise output from the digital SRAM macro, the non-ideal output from the RRAM macro will be compensated. In this way, we achieve digital-assisted analog in-memory computing. We also designed a silicon prototype of the proposed hybrid IMC architecture in the 65nm CMOS process to demonstrate its efficacy. Our hybrid IMC architecture, evaluated through simulation on ResNet-20 with CIFAR-10, achieves a post-mapping testing accuracy to 91.15%, higher to that of the RRAM macro with 3-bit ADC, while requiring 1.19× smaller area and 1.90× less average power.