Device and circuit design issues in SOI technology

Abstract

Partially-Depleted deep sub-micron CMOS on SOI technology is becoming a mainstream technology. This technology offers 20-35% performance gain over a bulk technology implemented with the same lithography. This paper first reviews the partially-depleted SOI device and describes reasons why it was chosen over fully depleted SOI device. Next the sources of performance gain on SOI are reviewed. SOI-unique circuit and technology issues that a designer must consider and account for are discussed next. Finally, a low-power application of SOI is reviewed.